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ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCATM and H.110
Data Sheet Features
* Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces Supports Telcordia GR-1244-CORE Stratum 3/4/4E Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs Provides a range of clock outputs: 1.544 MHz (DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz, and 19.44 MHz (SDH), and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz, and a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3) Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Holdover frequency accuracy of 1x10-8 Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
OSCi OSCo TIE_CLR
November 2005
Ordering Information
ZL30105QDG ZL30105QDG1 64 pin TQFP Trays 64 pin TQFP* Trays Bake & Drypack * Pb Free Matte Tin
* * * *
-40C to +85C * * Less than 0.6 nspp intrinsic jitter on all output clocks and frame pulses Manual or Automatic hitless reference switching between any combination of valid input reference frequencies Provides Lock, Holdover and selectable Out of Range indication Simple hardware control interface Selectable external master clock source: Clock Oscillator or Crystal
*
* * *
* * * *
Applications
* Synchronization and timing control for multi-trunk SDH and T1/E1 systems such as DSLAMs, Gateways and PBXs Clock and frame pulse source for AdvancedTCATM- and other time division multiplex (TDM) buses
LOCK OUT_SEL2
*
FASTLOCK
Master Clock REF0 REF1 REF2 REF2_SYNC REF_FAIL0 REF_FAIL1 REF_FAIL2 REF_SEL1:0 RST State Machine Reference Monitor
TIE Corrector Enable Mode Control
MUX
TIE Corrector Circuit
Virtual Reference
DPLL
E1 Synthesizer
DS1 Synthesizer SDH Synthesizer Programmable Synthesizer IEEE 1149.1a TCK TDI TMS TDO
Frequency Select MUX
C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o F16o C1.5o C3o C19o F2ko C6/8.4/34/44o OUT_SEL1:0
TRST
MODE_SEL1:0
HMS
HOLDOVER
SEC_MSTR
APP_SEL1:0
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30105
Description
Data Sheet
The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to a system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock and slave-clock outputs even in the presence of high network jitter. The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.
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Zarlink Semiconductor Inc.
ZL30105 Table of Contents
Data Sheet
1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Reference Select Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Application Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Loop Filter and Limiter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.4 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.1 Manual Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.2 Automatic Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.2.1 Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range . . . . . . . . . . . . . . . . . 26 4.6 Clock Redundancy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7 Pull-in Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.8 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 Clock Redundancy System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Zarlink Semiconductor Inc.
ZL30105 Table of Contents
Data Sheet
7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Zarlink Semiconductor Inc.
ZL30105 List of Figures
Data Sheet
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - DS1 Out-of-Range Thresholds for APP_SEL1:0=00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6 - E1 Out-of-Range Thresholds for APP_SEL=01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - REF2_SYNC Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18 - Examples of REF2 & REF2_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19 - Clock Redundancy with Two Independent Timing Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 20 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 22 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 23 - Typical Clocking Architecture of an ECTF H.110 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 24 - Typical Clocking Architecture of a PICMG AdvancedTCATM System . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 25 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 26 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 27 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 28 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 29 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 30 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Zarlink Semiconductor Inc.
ZL30105
1.0 Change Summary
Data Sheet
Changes from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this current issue. Page 1 33 Item Features Section 6.1 Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note.
Changes from October 2004 Issue to July 2005 Issue. Page, section, figure and table numbers refer to this current issue. Page 9 38 Item RST pin Table "DC Electrical Characteristics*" Change Specified clock and frame pulse outputs forced to high impedance Corrected Schmitt trigger levels
Changes from June 2004 Issue to October 2004 Issue. Page, section, figure and table numbers refer to this current issue. Page 1 7 35 38 38 Item Text Figure 2 Section 6.4 Table "Absolute Maximum Ratings*" Table "DC Electrical Characteristics*" Change Jitter changed to 24 ps from 20 ps Added note specifying not e-Pad Corrected time-constant of example reset circuit Corrected package power rating Corrected current consumption Corrected Schmitt trigger Vt- levels Corrected output voltage note to reflect two pad strengths Pulse widths corrected. Updated Min. Max. values.
38 41
Section 7.1 Table "AC Electrical Characteristics* Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 26)." Section 7.2
48 50
Changed jitter numbers
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Zarlink Semiconductor Inc.
ZL30105
2.0
2.1
Data Sheet
Physical Description
Pin Connections
F4/F65o F16o AGND IC REF_SEL0 REF_SEL1 REF0 REF1 REF2 REF2_SYNC SEC_MSTR APP_SEL0 VDD IC TIE_CLR FASTLOCK
F8/F32o C16o C2o AVDD AVDD C8/C32o C4/C65o AGND AGND C19o F2ko AVDD AVDD AVCORE AGND AGND
48 50 30 52 28 54 26 56 58 22 60 20 62 18 64 2 4 6 8 10 12 14 16 46 44 42 40 38 36 34
32
ZL30105
24
C1.5o C3o C6/8.4/34/44o AVDD OUT_SEL0 OUT_SEL1 OUT_SEL2 VDD APP_SEL1 GND IC OSCi OSCo RST MODE_SEL1 MODE_SEL0
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30105 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30105 does not use the e-Pad TQFP.
GND VCORE LOCK HOLDOVER REF_FAIL0 REF_FAIL1 REF_FAIL2 TDO TMS TRST TCK VCORE GND AVCORE TDI HMS
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Zarlink Semiconductor Inc.
ZL30105
2.2 Pin Description
Name GND VCORE LOCK HOLDOVER REF_FAIL0 Ground. 0 V Positive Supply Voltage. +1.8 VDC nominal Description
Data Sheet
Pin # 1 2 3 4 5
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected input reference. Holdover (Output). This output goes to a logic high whenever the PLL goes into holdover mode. Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. Positive Supply Voltage. +1.8 VDC nominal Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30105 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on this pin will cause the ZL30105 to measure a new delay for its TIE corrector circuit thereby minimizing the output phase movement when it transitions from Holdover or Freerun mode to Normal mode.
6
REF_FAIL1
7
REF_FAIL2
8 9
TDO TMS
10
TRST
11 12 13 14 15
TCK VCORE GND AVCORE TDI
16
HMS
17 18
MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of operation, see Table 4 on page 21. MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description.
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Pin # 19 Name RST Description
Data Sheet
Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be forced into high impedance. Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. Internal Connection. Leave unconnected. Ground. 0 V Application Selection 1 (Input). This input combined with APP_SEL0 selects the application that the ZL30105 is optimized for, see Table 1 on page 20. Positive Supply Voltage. +3.3 VDC nominal Output Selection 2 (Input). This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 21. Output Selection 1 (Input). This input combined with OUT_SEL0 selects the signals on the combined output clock pin C6/8.4/34/44o, see Table 3 on page 21. Output Selection 0 (Input). See OUT_SEL1 description. Positive Analog Supply Voltage. +3.3 VDC nominal
20
OSCo
21
OSCi
22 23 24 25 26 27 28 29 30
IC GND APP_SEL1 VDD OUT_SEL2 OUT_SEL1 OUT_SEL0 AVDD
C6/8.4/34/44o Clock 6.312 MHz, 8.448 MHz, 34.368 MHz or 44.736 MHz (Output). This output is used in DS2, E2, E3 or DS3 applications. The output frequency is selected via the OUT_SEL1 and OUT_SEL0 pins, see Table 3 on page 21. C3o C1.5o Clock 3.088 MHz (Output). This output is used in DS1 applications. Clock 1.544 MHz (Output). This output is used in DS1 applications. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels.
31 32
33 34 35 36 37 38 39 40 41
AGND AGND AVCORE AVDD AVDD F2ko C19o AGND AGND
Analog Ground. 0 V Analog Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Multi Frame Pulse (Output). This is a 2 kHz 51 ns active high framing pulse, which marks the beginning of a multi frame. Clock 19.44 MHz (Output). This output is used in SDH applications. Analog Ground. 0 V Analog Ground. 0 V
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Zarlink Semiconductor Inc.
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Pin # 42 Name C4/C65o Description
Data Sheet
Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL2 pin, see Table 3 on page 21. Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI operation at 8.192 Mb/s or for operation with a 32.768 MHz clock. The output frequency is selected via the OUT_SEL2 pin, see Table 3 on page 21. In C8 mode, this clock output pad uses an included Schmitt input as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels.
43
C8/C32o
44 45 46
AVDD AVDD C2o
Positive Analog Supply Voltage. +3.3 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048 Mbit/s. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels.
47
C16o
Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a 16.384 MHz clock. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels.
48
F8/F32o
Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse or it is an 8 kHz 31 ns active high framing pulse, which marks the beginning of a frame. The pulse width is selected via the OUT_SEL2 pin, see Table 3 on page 21. Frame Pulse ST-BUS 2.048 Mbit/s or ST-BUS at 65.536 MHz clock (Output). This output is an 8 kHz 244 ns active low framing pulse which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048 Mbit/s and 4.096 Mbit/s. Or this output is an 8 kHz 15 ns active low framing pulse, typically used for ST-BUS operation with a clock rate of 65.536 MHz. The pulse width is selected via the OUT_SEL2 pin, see Table 3 on page 21. Frame Pulse ST-BUS 8.192 Mbit/s (Output). This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mbit/s. Analog Ground. 0 V Internal Connection. Connect this pin to ground. Reference Select 0 (Input/Output). In the manual mode of operation, REF_SEL0 is an input. As an input REF_SEL0 combined with REF_SEL1 selects the reference input that is used for synchronization, see Table 6 on page 24. In the Automatic mode of operation, REFSEL0 is an output indicating which of the input references is the being selected. This pin is internally pulled down to GND. Reference Select 1 (Input/Output). See REF_SEL0 pin description. Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally pulled down to GND.
49
F4/F65o
50
F16o
51 52 53
AGND IC REF_SEL0
54 55
REF_SEL1 REF0
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Zarlink Semiconductor Inc.
ZL30105
Pin # 56 57 58 Name REF1 REF2 REF2_SYNC Description Reference (Input). See REF0 pin description. Reference (Input). See REF0 pin description.
Data Sheet
REF2 Synchronization Frame Pulse (Input). This is the 2 kHz or 8 kHz (multi) frame pulse synchronization input associated with the REF2 reference. While the PLL is locked to the REF2 input reference the output (multi) frame pulses are synchronized to this input. This pin is internally pulled down to GND. Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary Master mode of operation with 1.8 Hz or 3.6 Hz DPLL loop filter bandwidth. A logic high selects Secondary Master mode which forces the PLL to clear its TIE corrector circuit and lock to the selected reference using a high bandwidth loop filter and a phase slope limiting of 9.5 ms/s. Application Selection (Input). See APP_SEL1 pin description. Positive Supply Voltage. +3.3 VDC nominal Internal Connection. Connect to GND. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase. Fast Lock (Input). Set temporarily high to allow the ZL30105 to quickly lock to the input reference (one second locking time).
59
SEC_MSTR
60 61 62 63 64
APP_SEL0 VDD IC TIE_CLR FASTLOCK
3.0
Functional Description
The ZL30105 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization signals to interface circuits for the following types of primary rate digital transmission links, see Table 1: * * * * DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E E1 compliant with ITU-T G.703 and ETSI ETS 300 011 PDH compliant with Telcordia GR-1244-CORE Stratum 3 SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Figure 1 is a functional block diagram of the ZL30105 which is described in the following sections.
3.1
Reference Select Multiplexer (MUX)
The ZL30105 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs. The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF2_SYNC input. This feature supports the implementation of Primary and Secondary Master system clocks in AdvancedTCA or H.110 systems.
3.2
Reference Monitor
The input references are monitored by three independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
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Zarlink Semiconductor Inc.
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Data Sheet
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. * Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock is within the selected accuracy range, see Table 1. Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.
* * *
Reference Frequency Detector REF0 / REF1 / REF2
OR
REF_FAIL0 / REF_FAIL1 / REF_FAIL2
Precise Frequency Monitor
OR
REF_OOR
Reference select state machine
REF_SEL1:0
Coarse Frequency Monitor
dis/requalify timer
Single Cycle Monitor
OR
REF_DIS Mode select state machine REF_OOR = reference out of range. REF_DIS= reference disrupted. Both are internal signals.
HOLDOVER
Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable.
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Zarlink Semiconductor Inc.
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SCM or CFM failure SCM or CFM failure
Data Sheet
REF0
dis/requalify timer on REF0 2.5 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 REF0 REF1 10 s
Figure 4 - Behaviour of the Dis/Re-qualify Timer
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Data Sheet
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. If the device is set to Automatic mode (MODE_SEL1:0=11), then the state machine does not immediately switch to another reference. If the single cycle and/or coarse frequency failures persist for more than 2.5 s or the precise frequency monitor detects a failure, then the state machine will switch to another valid reference if that is available. If there no other reference available, it stays in Holdover mode. The precise frequency monitor's failure thresholds are selected with the APP_SEL pins based on the ZL30105 applications, see Table 1. Figure 5, Figure 6 and Figure 7 show the out of range limits for various master clock accuracies. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
C20 Clock Accuracy C20 0 ppm
-83 -64 0 64 83
Out of Range In Range Out of Range In Range
96 115
C20 +32 ppm
-51 -32 32
C20 -32 ppm
-115 -96 -32 32 51
Out of Range In Range Frequency offset [ppm]
-100 C20: 20 MHz master oscillator clock
-75
-50
-25
0
25
50
75
100
Figure 5 - DS1 Out-of-Range Thresholds for APP_SEL1:0=00
C20 Clock Accuracy C20 0 ppm
-130 -100 0 100 130
Out of Range In Range C20 Out of Range
150 180
+50 ppm
-80 -50 50
In Range Out of Range
C20 -50 ppm
-180 -150 -50 50 80
In Range Frequency offset [ppm]
-200 C20: 20 MHz master oscillator clock
-150
-100
-50
0
50
100
150
200
Figure 6 - E1 Out-of-Range Thresholds for APP_SEL=01
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Data Sheet
C20 Clock Accuracy C20 0 ppm
-12 -9.2 0 9.2 12
Out of Range In Range C20 Out of Range In Range
13.8 16.6
+4.6 ppm
-7.4 -4.6 4.6
C20 -4.6 ppm
-16.6 -13.8 -4.6 4.6 7.4
Out of Range In Range
-15 C20: 20 MHz master oscillator clock
-10
-5
0
5
10
15
Frequency offset [ppm]
Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11 In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also monitored for failure (see Figure 8). Sync Ratio Monitor (SRM): This monitor detects if the REF2_SYNC signal is a 2 kHz or an 8 kHz signal. It also checks the number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the integrity of the REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2 reference clock in a single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2 and REF2_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2 reference will be used for synchronization.
REF2_SYNC REF2 REF2 frequency SYNC Reference Monitor Circuit
to DPLL
Figure 8 - REF2_SYNC Reference Monitor
3.3
Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from Holdover mode to Normal mode. On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it recovers from Holdover mode.
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Zarlink Semiconductor Inc.
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Data Sheet
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown in Figure 26. The speed of the phase alignment correction is limited by the selected loop filter bandwidth and the phase slope limit (see Table 2). Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously; in that case the output clocks will always align with the selected input reference. This is illustrated in Figure 9. TIE_CLR = 0
locked to REF0 REF0 REF0
TIE_CLR = 1
locked to REF0
REF1
REF1
Output Clock
Output Clock
locked to REF1 REF0 REF0
locked to REF1
REF1
REF1
Output Clock
Output Clock
Figure 9 - Timing Diagram of Hitless Reference Switching The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode. (see Figure 10). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode. This causes accumulation of phase in network elements. In both cases the PLL's output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30105 is always hitless unless TIE_CLR is kept low continuously.
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Zarlink Semiconductor Inc.
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HMS = 0
Normal mode REF REF
Data Sheet
HMS = 1
Normal mode
Output Clock
Output Clock
Phase drift in Holdover mode REF REF
Phase drift in Holdover mode
Output Clock
Output Clock
Return to Normal mode REF REF
Return to Normal mode
Output Clock
Output Clock
TIE_CLR=0 REF REF
TIE_CLR=0
Output Clock
Output Clock
Figure 10 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When ten Normal to Holdover to Normal mode transitions occur and in each case the Holdover mode was entered for 2 seconds then the accumulated phase change (MTIE) could be as large as 330 ns. Phaseholdover_drift = 0.01 ppm x 2 s = 20 ns Phasemode_change = 0 ns + 13 ns = 13 ns Phase10 changes = 10 x (20 ns + 13 ns) = 330 ns
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Zarlink Semiconductor Inc.
ZL30105
where: 0.01 ppm is the accuracy of the Holdover mode
Data Sheet
0 ns is the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode 13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode when a new TIE corrector value is calculated
HMS=0: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode was entered for 2 seconds, then the overall MTIE would be 20 ns. As the delay value for the TIE corrector circuit is not updated, there is no 13 ns measurement error at this point. The phase can still drift for 20 ns when the PLL is in Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the phase is not accumulated.
3.4
Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30105 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 11. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin.
Lock Detector
Virtual Reference from TIE Corrector Circuit
LOCK
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator
DPLL Reference to Frequency Synthesizer
REF2_SYNC frame pulse
State Select from Control State Machine
Feedback signal from Frequency Select MUX feedback frame pulse; F8o or F2ko
Figure 11 - DPLL Block Diagram Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the feedback signal and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the limiter circuit. Limiter - the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope compliant with the applicable standards. The phase slope limit is dependent on the APP_SEL1:0 and SEC_MSTR pins and is listed in Table 2. Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 1.8 Hz or 3.6 Hz, suitable to provide Primary Master timing. When Secondary Master mode is selected (SEC_MSTR=1), the filter bandwidth is set to 922 Hz. For stability reasons, the loop filter bandwidth for 2 kHz and 8 kHz reference inputs is limited to a maximum of 14 Hz and 58 Hz respectively.
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Data Sheet
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30105. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in Normal Mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before the ZL30105 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into Holdover mode (auto or manual), the LOCK pin will initially stay high for 1 s in Primary Master mode. In Secondary Master mode, LOCK remains high for 0.1 s. If at that point the DPLL is still in holdover mode, the LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full lock-time duration. In Freerun mode the LOCK pin will go low immediately.
3.5
Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads.
3.6
State Machine
As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30105 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS.
3.7
Master Clock
The ZL30105 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.
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4.0
4.1
Data Sheet
Control and Modes of Operation
Application Selection
APP_SEL 00 01 10 11 Application DS1 E1 PDH Stratum 3 SDH Applicable Standard ANSI T1.403 Telcordia GR-1244-CORE Stratum 4/4E ITU-T G.703 ETSI ETS 300 011 Telcordia GR-1244-CORE Stratum 3 ITU-T G.813 Option 1 Telcordia GR-253-CORE Out Of Range Limits 64 - 83 ppm 100 - 130 ppm 9.2 - 12 ppm 9.2 - 12 ppm
Table 1 - Application Selection and the Out of Range Limits
4.2
Loop Filter and Limiter Selection
The loop filter and limiter settings are selected through the APP_SEL and SEC_MSTR pins, see Table 2. The maximum loop filter bandwidth is also dependent on the frequency of the currently selected reference (REF0/1/2). Phase Slope Limiting 61 /s 7.5 /s 9.5 ms /s 9.5 ms /s 9.5 ms /s
APP_SEL 00, 01, 10 11 00, 01, 10, 11
SEC_MSTR 0 0 1
Detected REF Frequency any any 2 kHz 8 kHz 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz
Loop Filter Bandwidth 1.8 Hz 3.6 Hz 14 Hz 58 Hz 922 Hz
Table 2 - Loop Filter and Limiter Settings
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Zarlink Semiconductor Inc.
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4.3 Output Clock and Frame Pulse Selection
Data Sheet
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two groups controlled by the OUT_SEL2:0 pins, see Table 3. OUT_SEL2 0 1 OUT_SEL1:0 00 01 10 11 C6o C8.4o C34o C44o Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin Generated Clocks C2o, C4o, C8o, C16o C2o, C16o, C32, C65o Generated Frame Pulses F4o, F8o, F16o F16o, F32o, F65o
4.4
Modes of Operation
The ZL30105 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one mode to the other is controlled by an external controller. The ZL30105 can be configured to automatically select a valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of operation, a state machine controls selection of references (REF0 or REF1) used for synchronization. MODE_SEL1 0 0 1 1 MODE_SEL0 0 1 0 1 Mode Normal (with automatic Holdover) Holdover Freerun Automatic (Normal with automatic Holdover and automatic reference switching) Table 4 - Operating Modes
4.4.1
Freerun Mode
Freerun mode is typically used when an independent clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun mode, the ZL30105 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32 ppm output clock is required, the master clock must also be 32 ppm. See Applications - Section 6.2, "Master Clock".
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Zarlink Semiconductor Inc.
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4.4.2 Holdover Mode
Data Sheet
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30105 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30105 output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched into Holdover Mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.01 ppm. Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm per C. So a 10 C change in temperature, while the ZL30105 is in Holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of 1 ppm. Which is much greater than the 0.01 ppm of the ZL30105. The other factor affecting the accuracy is large jitter on the reference input prior to the mode switch.
4.4.3
Normal Mode
Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal mode, the ZL30105 provides timing and frame synchronization signals, which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. When the ZL30105 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 12). If the ZL30105 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If the ZL30105 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then the ZL30105 will transition directly to Normal mode and it will align its output signals with its selected input reference (see Figure 10). If HMS=1 then the ZL30105 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the selected input reference will be maintained. When the ZL30105 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3) then its state machine will cause it to automatically go to Holdover mode. When the ZL30105 determines that its selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 12). If HMS=0 then the ZL30105 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 10). If HMS=1 then the ZL30105 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained. If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference selection state machine selected a different reference input, the ZL30105 goes into Holdover mode and returns to Normal mode through the TIE correction state regardless of the logic value on HMS pin. ZL30105 provides a fast lock pin (FASTLOCK), which, when set high enables the PLL to lock to an incoming reference within approximately 1 s.
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Data Sheet
Normal (HOLDOVER=0) REF_CH=1 REF_DIS=0 REF_DIS=1 REF_DIS=1 Holdover (HOLDOVER=1) (REF_DIS=0 and HMS=1) or REF_CH=1 TIE Correction (HOLDOVER=1)
RST
REF_DIS=0 and REF_CH=0 and HMS=0
REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14) or a change in the REF_SEL pins. REF_CH is an internal signal.
Figure 12 - Mode Switching in Normal Mode
4.4.4
Automatic Mode
The Automatic mode combines the functionality of the Normal mode (automatic Holdover) with automatic reference switching. The automatic reference switching is described in more detail in section 4.5.2, "Automatic Reference Switching".
4.5 4.5.1
Reference Switching Manual Reference Switching
In the manual modes of operation (MODE_SEL1:0 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30105 will perform a hitless reference switch. REF_SEL1 0 0 1 1 REF_SEL0 0 1 0 1 Input Reference Selected REF0 REF1 REF2 REF2
Table 5 - Manual Reference Selection When the REF_SEL inputs are used in Normal mode to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process.
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Data Sheet
REF_SEL
REF0
REF1
LOCK
Lock Time
Note: LOCK pin behaviour depends on phase and frequency offset of REF1.
Figure 13 - Reference Switching in Normal Mode
4.5.2
Automatic Reference Switching
In the automatic mode of operation (MODE_SEL1:0 = 11), the ZL30105 automatically selects a reference input that is not out-of-range (REF_OOR=0, see Figure 3). The state machine can only select REF0 or REF1; REF2 cannot be selected in the Automatic mode (see Figure 14). If the current reference (REF0 or REF1) used for synchronization fails, the state machine will switch to the other reference. If both references fail then the ZL30105 enters the Holdover mode without switching to another reference. When the ZL30105 comes out of reset or when REF2 is the current reference when the ZL30105 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection.
RST && REF_OOR0=0 REF_OOR0=0 && REF_OOR1=1 REF0 Reference REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0
RST && REF_OOR0=1 && REF_OOR1=0
REF1 Reference
REF_OOR0=1 && REF_OOR1=0
REF_OOR = reference out of range, see Figure 3. This is an internal signal.
REF2 Reference
Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11) In the automatic mode of operation, both pins REF_SEL1 and REF_SEL0 are configured as outputs. The logic level on the REF_SEL0 output indicates the current input reference being selected for synchronization (see Table 6). REF_SEL1 (output pin) 0 0 REF_SEL0 (output pin) 0 1
Input Reference REF0 REF1
Table 6 - The Reference Selection Pins in the Automatic Mode (MODE_SEL=11)
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Data Sheet
The mode selection state machine behaves differently in Automatic mode in that when both reference REF0 and reference REF1 are out of range (REF_OOR=1), the state machine will select the Holdover state. In Normal mode the reference out of range (REF_OOR) status is ignored by the state machine. This is illustrated in Figure 15.
Normal (HOLDOVER=0) REF_DIS=0 and REF_OOR=0 and REF_CH=0 and HMS=0 RST REF_DIS=1 or REF_OOR=1 Holdover (HOLDOVER=1) TIE Correction (HOLDOVER=1) REF_CH=1 REF_DIS=0 and REF_OOR=0
(REF_DIS=0 and REF_OOR=0 and HMS=1) or REF_CH=1 REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_OOR=1: Current selected reference out of range (see Figure 3). REF_OOR is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14). REF_CH is an internal signal.
Figure 15 - Mode Switching in Automatic Mode
4.5.2.1
Automatic Reference Switching - Coarse Reference Failure
When the currently-active input reference in Automatic mode fails in a coarse manner, the REF_DIS internal signal places the device in holdover, with the HOLDOVER pin and the REF_FAIL pin asserted. This can occur through triggering the Single Cycle Monitor, or the Coarse Frequency Monitor, in the Reference Monitor block. If the reference does not correct itself within the lock-disqualify duration (1 second) the LOCK pin is de-asserted. If the reference does not correct itself within the reference-disqualify duration (2.5 seconds) the HOLDOVER pin is de-asserted and the REF_SEL outputs indicate that the device has switched to the other reference. The LOCK pin remains de-asserted for the full lock-time duration, regardless of the phase and frequency offset of the old and new references. Figure 16 illustrates this process. If the reference corrects itself within the lock-disqualify duration (< 1 second) the HOLDOVER pin is de-asserted, and the REF_FAIL pin is de-asserted. The LOCK pin remains asserted. No reference switching takes place, and the REF_SEL outputs indicate that the device has remained locked to the old reference. If the reference does not correct itself within the lock-disqualify duration (1 second), but does correct itself within the reference-disqualify duration (< 2.5 seconds) the HOLDOVER pin is de-asserted, the REF_FAIL pin is de-asserted, and the REF_SEL outputs indicate that the device has remained locked to the old reference. However the LOCK pin is de-asserted, the lock-qualify timer is reset, and the LOCK pin remains de-asserted for the full lock-time duration. See 7.2, "Performance Characteristics" on page 46 for lock-time duration.
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SCM or CFM failure
Data Sheet
REF0
REF_DIS0 (internal signal) 2.5 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL LOCK REF0 REF1 10 s
1s
Lock Time
Note: this scenario is based on REF1 remaining good throughout the duration.
Figure 16 - Automatic Reference Switching - Coarse Reference Failure
4.5.2.2
Automatic Reference Switching - Reference Frequency Out-of-Range
When the currently-active input reference in Automatic mode fails through a subtle frequency offset, the REF_FAIL output is asserted as soon as the Precise Frequency Monitor indicates an out-of-range reference (10 to 20 seconds). The HOLDOVER output is briefly asserted (approximately three reference input cycles) and the REF_SEL outputs indicate that the device has switched to the other reference. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 17 illustrates this process.
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Frequency Precision failure
Data Sheet
REF0
10 to 20 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1
LOCK
Lock Time Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1.
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure
4.6
Clock Redundancy Support
In general, clock redundancy implies that the redundant timing card DPLL tracks the output clock and/or frame pulse of the active timing card DPLL. In case that the active timing card fails, the devices that use the active clock and/or frame pulse must be able to switch to the redundant clock and/or frame pulse without experiencing disruptions. Therefore the redundant signals must closely track the active signals. The ZL30105 supports this kind of clock redundancy in various ways; * Lock only to the active clock. The ZL30105 uses the 922 Hz loop filter bandwidth to closely track the active clock, even in the presence of jitter on the active clock. However the active and redundant frame pulse may not be aligned. Lock to the active frame pulse. Both the redundant clock and frame pulse will be aligned with the active clock and frame pulse. However the ZL30105 loop filter bandwidth is limited to 14 Hz (2 kHz active frame pulse) or 58 Hz (8 kHz active frame pulse). Therefore the redundant clock and frame pulse will not track the active frame pulse as closely in the presence of jitter on the active frame pulse as with a 922 Hz loop filter bandwidth. Lock to both the active clock and associated frame pulse. The ZL30105 uses the 922 Hz loop filter bandwidth and thereby track the active clock and frame pulse in the presence of jitter on the active signals. It will also align the redundant frame pulse with the active frame pulse.
*
*
The method of clock redundancy shown in Figure 19 is that the redundant timing card is frequency and phase locked to the active clock and frame pulse. The redundant card is configured as Secondary Master (SEC_MSTR=1) and continuously adjusts the phase of its output clocks and frame pulses to match that of the active clock and frame pulse. In this mode of operation, the bandwidth of the redundant timing card's DPLL is much larger than that of the active timing card's DPLL, 922 Hz versus 1.8 Hz. Therefore the redundant clocks and frame pulses will track the active clock and frame pulse closely even in the presence of the maximum tolerable input jitter and wander on the active timing card's reference input.
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Data Sheet
The method of synchronization using REF2 and REF2_SYNC is enabled as soon as a valid 2 kHz or 8 kHz frame pulse is detected on the REF2_SYNC input. The REF2_SYNC pulse must be generated from the clock that is present on the REF2 input. The ZL30105 checks the number of REF2 cycles in the REF2_SYNC period. If this is not the nominal number of cycles, the REF2_SYNC pulse is considered invalid. For example, if REF2 is a 8.192 MHz clock and REF2_SYNC is a 8 kHz frame pulse, then there must be exactly 1024 REF2 cycles in a REF2_SYNC period. If a valid REF2_SYNC pulse is detected, the ZL30105 will align the rising edges of the REF2 clock and the corresponding output clock such that the rising edge of the F8o/F32o output frame pulse is aligned with the frame boundary indicated by the REF2_SYNC signal. The rising edges of the REF2 and the corresponding output clock that are aligned, are the ones that lag the rising edges of the REF2_SYNC and the F8o pulses respectively. This is illustrated in Figure 18. Many combinations of the ZL30105 clock and frame pulse outputs can be used as REF2 and REF2_SYNC inputs. In general, the active low frame pulses F4o, F16o and F65o would be inverted first before used as a REF2_SYNC input.
REF2_SYNC = 8 kHz
REF2 = C8o aligned F8o C8o
REF2_SYNC = 2 kHz
REF2 = C19o aligned F2ko C19o
Figure 18 - Examples of REF2 & REF2_SYNC to Output Alignment
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Data Sheet
Active Timing Card
MODE_SEL1:0=11 SEC_MSTR=0
OSC
REF0 REF1
BITS 0 clock BITS 1 clock
Output Clocks ZL30105
REF2 REF2_SYNC
Redundant Frame Sync (optional) Redundant Clock Active Clock Active Frame Sync (optional)
REF2_SYNC REF2
BITS 0 clock BITS 1 clock
MODE_SEL1:0=00 REF_SEL1:0=10 SEC_MSTR=1
REF0 REF1
ZL30105 Output Clocks
OSC
Redundant Timing Card
Figure 19 - Clock Redundancy with Two Independent Timing Cards The following is an example of how active/redundant setup can be configured. The active timing card is set based on the desired application and is set to: * * * Primary master mode, SEC_MSTR=0 Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL) Automatic mode, MODE_SEL1:0=11 (allows device to auto-switch if reference fails)
The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock. The redundant timing card is set based on desired applications and is set to: * * * Normal (manual) mode, MODE_SEL1:0=00 REF2 and REF2_SYNC as the input reference, REF_SEL1=1 (forces redundant device to lock to output of active card) Secondary master mode, SEC_MSTR=1
The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock.
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Data Sheet
When the redundant timing card is switched to becoming the active timing card, the system controller should do the following: * * select Primary Master mode, SEC_MSTR=0 select Automatic mode, MODE_SEL1:0=11
The new active timing card will automatically select a valid input reference REF0 or REF1. If both input references are available and valid, then REF0 will be chosen over REF1. If the new active timing card should use the same input reference (REF0 or REF1) as the old active timing card used before it failed, The system controller should do the following instead: * * * * * select Holdover (manual) mode, MODE_SEL1:0=01 select Primary Master mode, SEC_MSTR=0 select the required reference (REF0 or REF1) as the input reference Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL) select Automatic mode, MODE_SEL1:0=11
It is recommended to maintain HMS=1 when switching from redundant to active through the Holdover mode, to eliminate output phase transients. When the active timing card is switched to becoming the redundant timing card, the system controller should do the following: * * * select Normal (manual) mode, MODE_SEL1:0=00 select Secondary Master mode, SEC_MSTR=1 select REF2 and REF2_SYNC as the input reference, REF_SEL1=1
The ZL30105 allows for the switch from Secondary Master mode to Primary Master mode with no frequency or phase hits on the output clocks. The switch from Primary Master mode to Secondary Master mode may introduce a phase transient on the output clocks as the TIE correction circuit is disabled to allow the Secondary master device to track the active clocks closely.
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5.0 Measures of Performance
Data Sheet
The following are some PLL performance indicators and their corresponding definitions.
5.1
Jitter
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter.
5.2
Jitter Generation (Intrinsic Jitter)
Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Jitter is usually measured with various bandlimiting filters depending on the applicable standards.
5.3
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards.
5.4
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 s/s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated). Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter).
5.5
Frequency Accuracy
The Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode.
5.6
Holdover Accuracy
Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30105, the storage value is determined while the device is in Normal Mode and locked to an external reference signal.
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5.7
Pull-in Range
Data Sheet
Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization.
5.8
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization.
5.9
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope is as the fractional change per time unit. For example; a phase slope of 61 s/s can also be specified as 61 ppm.
5.10
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
5.11
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period.
5.12
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state.
5.13
Lock Time
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: * * * * * initial input to output phase difference initial input to output frequency difference PLL loop filter bandwidth PLL phase slope limiter in-lock phase distance
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times.
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6.0 Applications
Data Sheet
This section contains ZL30105 application specific details for power supply decoupling, reset operation, clock and crystal operation.
6.1
Power Supply Decoupling
Jitter levels on the ZL30105 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30105 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178.
6.2
Master Clock
The ZL30105 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30105.
6.2.1
Clock Oscillator
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. 1 2 3 4 Frequency Tolerance Rise & fall time Duty cycle 20 MHz as required < 10 ns 40% to 60%
Table 7 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30105, and the OSCo output should be left open as shown in Figure 20.
ZL30105
OSCi
+3.3 V
+3.3 V 20 MHz OUT GND
0.1 F
OSCo No Connection
Figure 20 - Clock Oscillator Circuit
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6.2.2 Crystal Oscillator
Data Sheet
Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 21. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. A typical crystal oscillator specification and circuit is shown in Table 8 and Figure 21 respectively.
.
1 2 3 4 5 6
Frequency Tolerance Oscillation mode Resonance mode Load capacitance Maximum series resistance
20 MHz as required fundamental parallel as required 50
Table 8 - Typical Crystal Oscillator Specification
20 MHz OSCi
ZL30105
1 M
OSCo 100 1 H
The 100 resistor and the 1 H inductor may improve stability and are optional.
Figure 21 - Crystal Oscillator Circuit
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6.3 Power Up Sequence
Data Sheet
The ZL30105 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power up the 3.3 V supply fully first, then power up the1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1.8 V supply (e.g., by using a schottky diode or controlled slew rate)
6.4
Reset Circuit
A simple power up reset circuit with about a 60 s reset low time is shown in Figure 22. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns.
ZL30105 +3.3 V R 10 k RST RP 1 k
C 10 nF
Figure 22 - Power-Up Reset Circuit
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6.5 Clock Redundancy System Architecture
Data Sheet
Carrier-Class Telecommunications Equipment deployed in today's networks guarantee better than 99.999% operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted service is achieved by fully redundant architectures with hot swappable cards like an ECTF H.110 or a PICMG AdvancedTCA compliant system. Timing for these types of systems can be generated by the ZL30105 which supports primary/secondary master timing protection switching. The architecture shown in Figure 23 and Figure 24 is based on the ZL30105 being deployed on two separate timing cards; the primary master timing card and the secondary master timing card. In normal operation the primary master timing card receives synchronization from the network and provides timing for the whole system. The redundant secondary master timing card is phase locked to the backplane clock and frame pulse through its REF2 and REF2_SYNC inputs. These two designated inputs allow the secondary master timing card to track the primary master timing card clocks with minimal phase skew. When the primary master timing card fails unexpectedly (this failure is not related to reference failure) then all switch cards or line cards will detect this failure and they will switch to the timing supplied by the secondary master timing card. The secondary master timing card will be promoted to primary master and switch from using the REF2 and REF2_SYNC inputs to one of the REF0 or REF1 inputs.
Backplane
CT_C8_A CT_FRAME_A CT_NETREF_2 CT_NETREF_1 CT_FRAME_B CT_C8_B
ZL30105
REF0 REF1 REF2 REF2_SYNC SEC_MSTR C8o F8o
Switch Card or Line Card
0 Master/Slave Control
Primary Master Timing Card
Switch Card or Line Card ZL30105
REF0 REF1 REF2 REF2_SYNC SEC_MSTR C8o F8o
1 Master/Slave Control
Secondary Master Timing Card
Figure 23 - Typical Clocking Architecture of an ECTF H.110 System
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Data Sheet
Backplane
CLK2A CLK1A CLK3A CLK3B CLK1B CLK2B
ZL30105
REF0 REF1 REF2 REF2_SYNC SEC_MSTR C19o F8o
ZL30106 Line Card PLL
0 Master/Slave Control
Primary Master Timing Card
ZL30105
REF0 REF1 REF2 REF2_SYNC SEC_MSTR C19o F8o
ZL30106 Line Card PLL
1 Master/Slave Control
Secondary Master Timing Card
Figure 24 - Typical Clocking Architecture of a PICMG AdvancedTCATM System
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7.0
7.1
Data Sheet
Characteristics
AC and DC Electrical Characteristics
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 8 Supply voltage Core supply voltage Voltage on any digital pin Voltage on OSCi and OSCo pin Current on any pin Storage temperature TQFP 64 pin package power dissipation ESD rating Symbol VDD_R VCORE_R VPIN VOSC IPIN TST PPD VESD -55 Min. -0.5 -0.5 -0.5 -0.3 Max. 4.6 2.5 6 VDD + 0.3 30 125 500 2 Units V V V V mA C mW kV
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated.
Recommended Operating Conditions* Characteristics 1 2 3 Supply voltage Core supply voltage Operating temperature Sym. VDD VCORE TA Min. 2.97 1.62 -40 Typ. 3.30 1.80 25 Max. 3.63 1.98 85 Units V V C
* Voltages are with respect to ground (GND) unless otherwise stated.
DC Electrical Characteristics* Characteristics 1 2 3 4 5 6 7 8 9 Supply current with: OSCi = 0 V OSCi = Clock, OUT_SEL=000 OSCi = Clock, OUT_SEL=111 Core supply current with: OSCi = 0 V OSCi = Clock Schmitt trigger Low to High threshold point Schmitt trigger High to Low threshold point Input leakage current High-level output voltage Sym. IDDS IDD IDD ICORES ICORE Vt+ VtIIL VOH Min. 1 30 45 0 14 1.43 0.8 -105 2.4 Max. 8 60 78 25 22 1.85 1.10 105 Units mA mA mA A mA V V A V VI = VDD or 0 V IOH = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs All device inputs are Schmitt trigger type. outputs loaded with 30 pF Notes
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DC Electrical Characteristics* Characteristics 10 Low-level output voltage Sym. VOL Min. Max. 0.4 Units V
Data Sheet
Notes IOL = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated.
AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 25). Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low Sym. VT VHM VLM CMOS 0.5 * VDD 0.7 * VDD 0.3 * VDD Units V V V
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated.
Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT V LM
Figure 25 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics* - Input timing for REF0, REF1 and REF2 references (see Figure 26). Characteristics 1 2 3 4 5 6 7 8 2 kHz reference period 8 kHz reference period 1.544 MHz reference period 2.048 MHz reference period 8.192 MHz reference period 16.384 MHz reference period 19.44 MHz reference period reference pulse width high or low Symbol tREF2kP tREF8kP tREF1.5P tREF2P tREF8P tREF16P tREF8kP tREFW Min. 484 121 338 263 63 38 38 15 Typ. 500 125 648 488 122 61 51 Max. 515 128 950 712 175 75 75 Units s s ns ns ns ns ns ns
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-of-Range limits.
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Data Sheet
tREFP tREFW REF0/1/2 tREFW
output clock with the same frequency as REF
tREFD
tREF8kD, tREF_F8D F8_32o
Figure 26 - REF0/1/2 Input Timing and Input to Output Timing AC Electrical Characteristics* - Input timing for REF2_SYNC (see Figure 27). Characteristics 1 2 3 4 5 REF2_SYNC pulse width high or low REF2_SYNC lag time REF2_SYNC lead time REF2_SYNC frequency 2 kHz 8 kHz 2 kHz 8 kHz 2 kHz, 8 kHz Symbol tSYNC_LD tSYNC_LD tSYNC_LG tSYNC_LG tSYNC_W 15 Min. Max. 0 12 tREFP - 15 tREFP - 28 Units ns ns ns ns ns tREFP = minimum period of REF2 clock tREFP = minimum period of REF2 clock Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 18, "Examples of REF2 & REF2_SYNC to Output Alignment" on page 28 for further explanation.
edge used for alignment tREFP REF2 tSYNC_LD REF2_SYNC tSYNC_W Note: REF2 can be 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. REF2_SYNC can be 2 kHz or 8 kHz. tSYNC_LG
Figure 27 - REF2_SYNC Timing
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ZL30105
Data Sheet
AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 26). Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 2 kHz reference input to F2ko delay 2 kHz reference input to F8/F32o delay 8 kHz reference input to F8/F32o delay 1.544 MHz reference input to C1.5o delay 1.544 MHz reference input to F8/F32o delay 2.048 MHz reference input to C2o delay 2.048 MHz reference input to F8/F32o delay 8.192 MHz reference input to C8o delay 8.192 MHz reference input to F8/F32o delay 16.384 MHz reference input to C16o delay 16.384 MHz reference input to F8/F32o delay 19.44 MHz reference input to C19o delay 19.44 MHz reference input to F8/F32o delay Symbol tREF2kD tREF2k_F8D tREF8kD tREF1.5D tREF1.5_F8D tREF2D tREF2_F8D tREF8D tREF8_F8D tREF16D tREF16_F8D tREF19D tREF19_F8D Min. 0 -27.2 -0.3 -1.2 -1.1 -1.2 -0.6 -2.0 -1.0 -1.1 29.0 0.2 -1.7 Max. 1.2 -26.5 2.0 0.2 0.9 0 0.8 0.1 1.8 1.9 30.6 1.1 -1.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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ZL30105
AC Electrical Characteristics* - E1 output timing (see Figure 28). Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C2o delay C2o pulse width low F4o pulse width low F4o delay C4o pulse width low C4o delay F8o pulse width high C8o pulse width low C8o delay F16o pulse with low F16o delay C16o pulse width low C16o delay F32o pulse width high C32o pulse width low C32o delay F65o pulse with low F65o delay C65o pulse width low C65o delay Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC2D tC2L tF4L tF4D tC4L tC4D tF8H tC8L tC8D tF16L tF16D tC16L tC16D tF32H tC32L tC32D tF65L tF65D tC65L tC65D tOR tOF Min. -0.4 243.0 243.3 121.5 121.0 -0.3 121.6 60.3 -0.4 60.3 29.9 28.7 -0.5 30.0 14.7 -0.5 14.7 7.1 7.2 -1.0 1.1 1.2 Max. 0.3 244.1 244.3 122.2 122.4 1.1 123.5 61.3 0.3 61.2 30.8 30.8 1.5 32.1 15.5 0.5 15.5 8.0 8.1 1.0 2.0 2.3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
outputs loaded with 30 pF
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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Zarlink Semiconductor Inc.
ZL30105
Data Sheet
tF8H F8o tC2L C2o tF4L F4o tC4L C4o tC8L C8o
tF16D
tC2D
tF4D
tC4D
tC8D
F16o tC16L C16o
tF16L tC16D
tF32H F32o tC32L C32o tF65D tF65L tC65L C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. tC65D tC32D
F65o
Figure 28 - E1 Output Timing Referenced to F8/F32o
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Zarlink Semiconductor Inc.
ZL30105
AC Electrical Characteristics* - DS1 output timing (see Figure 29). Characteristics 1 2 3 4 5 6 C1.5o delay C1.5o pulse width low C3o delay C3o pulse width low Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC1.5D tC1.5L tC3D tC3L tOR tOF Min. -0.6 323.1 -0.7 161.1 1.1 1.2 Max. 0.6 324.0 0.5 162.0 2.0 2.3 Units ns ns ns ns ns ns
Data Sheet
Notes
outputs loaded with 30 pF
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
F8_32o tC1.5L C1.5o tC3L C3o tC3D tC1.5D
Figure 29 - DS1 Output Timing Referenced to F8/F32o AC Electrical Characteristics* - SDH output timing (see Figure 30). Characteristics 1 2 3 4 5 6 C19o delay C19o pulse width low F2ko delay F2ko pulse width high Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC19D tC19L tF2kD tF2kH tOR tOF Min. -1.0 25.0 25.0 51.1 1.1 1.2 Max. 0.5 25.8 26.6 51.8 2.0 2.3 Units ns ns ns ns ns ns outputs loaded with 30 pF Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
F8_32o tC19L C19o tF2D F2ko tF2kH tC19D
Figure 30 - SDH Output Timing Referenced to F8/F32o
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Zarlink Semiconductor Inc.
ZL30105
AC Electrical Characteristics* - DS2, E2, E3 and DS3 Output Timing (see Figure 31). Characteristics 1 2 3 4 5 6 7 8 9 10 C6o delay C6o pulse width low C8.4o delay C8.4o pulse width low C34o delay C34o pulse width low C44o delay C44o pulse width low Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC6D tC6L tC8.4D tC8.4L tC34D tC34L tC44D tC44L tOR tOF Min. -0.70 78.5 -0.8 58.4 -0.5 13.5 -1.0 10.4 1.1 1.2 Max. 0.70 79.3 0.8 59.2 0.5 14.6 0.5 11.2 2.0 2.3 Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
outputs loaded with 30 pF
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
F8_32o tC44L C44o tC34L C34o tC8.4L C8.4o tC6L C6o tC6D tC8.4D tC34D
tC44D
Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o
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Zarlink Semiconductor Inc.
ZL30105
AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 2 3 4 5 6 7 Oscillator Tolerance - DS1 Oscillator Tolerance - E1 Oscillator Tolerance - PDH Stratum 3 Oscillator Tolerance - SDH Duty cycle Rise time Fall time Min. -32 -50 -4.6 -4.6 40 Max. +32 +50 +4.6 +4.6 60 10 10 Units ppm ppm ppm ppm % ns ns Notes
Data Sheet
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
7.2
Performance Characteristics
Performance Characteristics* - Functional Characteristics 1 2 3 Holdover accuracy Holdover stability Freerun accuracy Capture range 4 5 DS1 / E1 PDH Stratum 3 / SDH Reference Out of Range Threshold (including hysteresis) 6 7 8 DS1 E1 PDH Stratum 3 / SDH Lock Time 9 DS1 (1.8 Hz filter - all reference frequencies) 40 40 s 64 ppm frequency offset, SEC_MSTR = 0, HMS = 1, TIE_CLR = 1, and FASTLOCK=0. -64 -83 -100 -130 -9.2 -12 +64 +83 +100 +130 +9.2 +12 ppm ppm ppm The 20 MHz master clock oscillator set at 0 ppm The 20 MHz master clock oscillator set at 0 ppm The 20 MHz master clock oscillator set at 0 ppm -130 -12 +130 +12 ppm ppm The 20 MHz master clock oscillator set at 0 ppm The 20 MHz master clock oscillator set at 0 ppm Min. Max. 0.01 0 0 Units ppm ppm ppm Determined by stability of the 20 MHz master clock oscillator Determined by accuracy of the 20 MHz master clock oscillator Notes
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Zarlink Semiconductor Inc.
ZL30105
Performance Characteristics* - Functional (continued) Characteristics 10 E1 (1.8 Hz filter - all reference frequencies) PDH Stratum 3 (1.8 Hz filter - all reference frequencies) SDH (3.6 Hz filter - all reference frequencies) SEC_MSTR = 1 (14 Hz filter - 2 kHz reference) SEC_MSTR = 1 (58 Hz filter - 8 kHz reference) SEC_MSTR = 1 (922 Hz filter 1.544 MHz and greater reference frequencies) fast lock Min. 40 Max. 50 Units s Notes
Data Sheet
100 ppm frequency offset, SEC_MSTR = 0, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 9.2 ppm frequency offset, SEC_MSTR = 0, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 9.2 ppm frequency offset, SEC_MSTR = 0, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 Up to 100 ppm frequency offset, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 Up to 100 ppm frequency offset, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 Up to 100 ppm frequency offset, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 Up to 100 ppm frequency offset, HMS = 1, TIE_CLR = 1, and FASTLOCK=1
11
48
50
s
12
40
40
s
13
25
25
s
14
15
15
s
15
1
1
s
16
1
1
s
Output Phase Continuity (MTIE) 17 18 19 Reference switching Switching from Normal mode to Holdover mode Switching from Holdover mode to Normal mode Output Phase Slope 20 21 22 DS1 / E1 / PDH Stratum 3 SDH SEC_MSTR=1: clock redundancy support 61 7.5 9.5 s/s s/s ms/s SEC_MSTR=0 SEC_MSTR=0 13 0 13 ns ns ns TIE_CLR=1 and HMS=1 TIE_CLR=1
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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Zarlink Semiconductor Inc.
ZL30105
Performance Characteristics*: Input Wander and Jitter Tolerance Conformance Input reference frequency 1 2 3 1.544 MHz 2.048 MHz 19.44 MHz Standard Telcordia GR-1244-CORE ITU-T G.823 ITU-T G.813
Data Sheet
Interface DS1 Line timing, DS1 External timing 2048 kbit/s Option 1
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics*: Output Jitter Generation - ANSI T1.403 conformance ANSI T1.403 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30105 maximum jitter generation Units
DS1 Interface 1 2 C1.5o (1.544 MHz) 8 kHz to 40 kHz 10 Hz to 40 kHz 0.07 UIpp 0.5 UIpp 45.3 324 0.30 0.32 nspp nspp
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics*: Output Jitter Generation - ITU-T G.747 conformance ITU-T G.747 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30105 maximum jitter generation Units
DS2 Interface 1 C6o (6.312 MHz) 10 Hz to 60 kHz 0.05 UIpp 7.92 0.20 nspp
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics*: Output Jitter Generation - ITU-T G.812 conformance ITU-T G.812 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30105 maximum jitter generation Units
E1 Interface 1
C2o (2.048 MHz)
20 Hz to 100 kHz
0.05 UIpp
24.4
0.36
nspp
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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Zarlink Semiconductor Inc.
ZL30105
Data Sheet
Performance Characteristics*: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Filter Limit in UI
(1 UI = 6.4 ns)
Signal OC-3 Interface 1 2 3 4 C19o
Equivalent limit in time domain
ZL30105 maximum jitter generation
Units
65 kHz to 1.3 MHz 12 kHz to1.3 MHz (Category II) 500 Hz to 1.3 MHz
0.15 UIpp 0.1 UIpp 0.01 UIrms 1.5 UIpp
0.96 0.64 64 9.65
0.22 0.22 24 0.22
nspp nspp psrms nspp
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics*: Measured Output Jitter - G.813 conformance (Option 1 and Option 2) ITU-T G.813 Jitter Generation Requirements Jitter Measurement Filter Limit in UI
(1 UI = 6.4 ns)
Signal
Equivalent limit in time domain
ZL30105 maximum jitter generation
Units
STM-1 Option 1 Interface 1 2 3 C19o C19o 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz 12 kHz to1.3 MHz 0.1 UIpp 0.5 UIpp 0.1 UIpp 0.64 3.22 0.64 0.22 0.22 0.22 nspp nspp nspp
STM-1 Option 2 Interface
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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Zarlink Semiconductor Inc.
ZL30105
Performance Characteristics* - Unfiltered Jitter Generation Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C1.5o (1.544 MHz) C2o (2.048 MHz) C3o (3.088 MHz) C4o (4.096 MHz) C6o (6.312 MHz) C8o (8.192 MHz) C8.4o (8.448 MHz) C16o (16.384 MHz) C19o (19.44 MHz) C32o (32.768 MHz) C34o (34.368 MHz) C44o (44.736 MHz) C65o (65.536 MHz) F2ko (2 kHz) F4o (8 kHz) F8o (8 kHz) F16o (8 kHz) F32o (8 kHz) F65o (8 kHz) Max. [nspp] 0.45 0.47 0.53 0.42 0.58 0.42 0.55 0.56 0.42 0.46 0.56 0.60 0.49 0.40 0.43 0.43 0.44 0.43 0.46 Notes
Data Sheet
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
8.0
References
AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group.
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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